Semiconductor integrated circuit (IC) fabrication involves forming multiple material layers with designed patterns on a semiconductor wafer. Each layer has to be aligned with previous layers such that the formed circuit can function properly. Various marks are used for this purpose. For example, alignment marks are used for alignment between a mask (a photo mask) and a semiconductor wafer. In another example, overlay marks are used to monitor overlay deviation between multiple layers on a wafer. As semiconductor technology continues progressing to circuits having smaller feature sizes, alignment requirements become more stringent. Therefore, it is desirable to have alignment marks that provide high signal intensity and measurement accuracy.